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11.1Gb/s Lane Extender
QLx111GRx
The QLx111GRx is a settable single-channel receive-side equalizer with extended functionality for advanced protocols operating with line rates up to 11.1Gb/s such as 10G Ethernet (10GBase-CR). The QLx111GRx compensates for the frequency dependent attenuation of copper twin-axial cables, extending the signal reach up to at least 10m on 28AWG cable. The small form factor, highly-integrated design is ideal for high-density data transmission applications including active copper cable assemblies. The equalizing filter within the QLx111GRx can be set to provide optimal signal fidelity for a given media and length. The compensation level for the filter is set by two external control pins. Operating on a single 1.2V power supply, the QLx111GRx enables per channel throughputs of 10Gb/s to 11.1Gb/s while supporting lower data rates including 8.5, 6.25, 5, 4.25, 3.125, and 2.5Gb/s. The QLx111GRx uses current mode logic (CML) input/output and is packaged in a 3mmx3mm 16 lead QFN. LOS support is included for module applications.
QLx111GRx
Features
* Supports data rates up to 11.1Gb/s * Low power (<135mW) * Low latency (<500ps) * Single channel equalizer in a 3mmx3mm QFN package for straight route-through architecture and simplified routing * Adjustable equalizer boost * Supports 64b/66b encoded data - long run lengths * Line silence preservation * 1.2V supply voltage * LOS support
Applications
* SFP+ active copper cable modules * QSFP active copper cable modules * 10G Ethernet (10GBase-CR) * XFI * 40G Ethernet (40GBase-CR4) * Fibre Channel * High-speed active cable assemblies * High-speed printed circuit board (PCB) traces
Benefits
* Thinner gauge cable * Extends cable reach greater than 3x * Improved BER
Typical Application Circuit
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
QLx111GRx
Ordering Information
PART NUMBER (Note) QLX111RIQT7 QLX111RIQSR PART MARKING QL111 QL111 TEMP. RANGE (C) 0 to +70 0 to +70 PACKAGE (Pb-Free) 16 Ld QFN 7" Prod. Tape & Reel; Qty 1,000 16 Ld QFN 7" Sample Reel; Qty 100 PKG. DWG. # L16.3x3B L16.3x3B
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
Pin Configuration
QLx111GRx (16 LD QFN) TOP VIEW
GND GND 13 12 VDD 11 OUT[P] 10 OUT[N] 9 5 GND 6 CP[A] 7 CP[B] 8 GND VDD LOS 14 DT 15
16 VDD 1 IN[P] 2 IN[N] 3 VDD 4
Pin Descriptions
PIN NAME VDD IN[P,N] CP[A,B] OUT[P,N] LOS DT PIN NUMBER 1, 4, 12, 9 2, 3 6, 7 11, 10 14 15 DESCRIPTION Power supply. 1.2V supply voltage. The use of parallel 100pF and 10nF decoupling capacitors to ground is recommended for each of these pins for broad high-frequency noise suppression. Equalizer 1 differential input, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. Control pins for setting the equalizer. CMOS logic inputs. Pins are read as a 2-digit number to set the boost level. Pins are internally pulled up and down through a 23k resistor. Equalizer differential output, CML. The use of 100nF low ESL/ESR MLCC capacitor with at least 6GHz frequency response is recommended. LOS indicator. High output when equalized In signal is below DT threshold. Open drain output internally pulled up to VDD with a 10k resistor. Detection Threshold. Reference DC voltage threshold for input signal power detection. Data output OUT is muted when the power of the equalized version of IN falls below the threshold. Tie to ground to disable electrical idle preservation and always enable the limiting amplifier.
GND
5, 8, 13, 16 Ground
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QLx111GRx
Absolute Maximum Ratings
Supply Voltage (VDD to GND) Voltage at All Input Pins . . . . ESD Rating High Speed Pins . . . . . . . . All Other Pins . . . . . . . . . . . . . . . . . . . . . . -0.3V to 1.3V . . . . . . . -0.3V to VDD + 0.3V . . . . . . . . . . . . . 1.5kV (HBM) . . . . . . . . . . . . . . 2kV (HBM)
Thermal Information
Operating Ambient Temperature Range . . . . . . 0C to +85C Storage Ambient Temperature Range . . . . -55C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . +125C Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
Operating Conditions
PARAMETER Supply Voltage Operating Ambient Temperature Bit Rate SYMBOL VDD TA NRZ data applied to any channel CONDITION MIN 1.1 0 2.5 TYP 1.2 25 MAX 1.3 70 11.1 UNITS V C Gb/s
Control Pin Characteristics Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise
noted. VDD = 1.1V to 1.3V, TA = 0C to +85C. PARAMETER Input LOW Logic Level Input HIGH Logic Level Output LOW Logic Level Output HIGH Logic Level Input Current SYMBOL VIL VIH VOL VOH DI, Clk, ENB DI, Clk, ENB LOS, DO LOS, DO Current draw on digital pin, i.e., CP[A,B], DI, Clk, ENB CONDITION MIN 0 750 0 1000 30 0 TYP 0 MAX 350 VDD 250 VDD 100 UNITS mV mV mV mV A
Electrical Specifications
PARAMETER Supply Current Cable Input Amplitude Range DC Differential Input Resistance DC Single-Ended Input Resistance Input Return Loss (Differential) Input Return Loss (Common Mode) Input Return Loss (Com. to Diff. Conversion) Output Amplitude Range Differential Output Impedance Output Return Loss (Differential) Output Return Loss (Common Mode)
Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +85C. CONDITION MIN TYP 111 Measured differentially at data source before encountering channel loss Measured on input channel IN Measured on input channel IN[P] or IN[N] 600 80 40 12 7 35 500 80 10 5 650 100 800 120 1200 100 50 1600 120 60 MAX UNITS mA mVP-P dB dB dB mVP-P dB dB 2 2 2 2 2 1 NOTES
SYMBOL IDD VIN
SDD11 SCC11 SDC11 VOUT
100MHz to 7.5GHz 100MHz to 7.5GHz 100MHz to 7.5GHz Measured differentially at OUT[P] and OUT[N] with 50 load on both output pins Measured on OUT
SDD22 SCC22
100MHz to 7.5GHz 100MHz to 7.5GHz
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Electrical Specifications
PARAMETER Output Return Loss (Com. to Diff. Conversion) Output Residual Deterministic Jitter Output Residual Deterministic Jitter Output Transition Time Propagation Delay LOS Assert Time Typical values are at VDD = 1.2V, TA = +25C, and VIN = 600mVP-P, unless otherwise noted. VDD = 1.1V to 1.3V, TA = 0C to +85C. (Continued) CONDITION 100MHz to 7.5GHz 10Gb/s; Up to 10m 28AWG standard twin-axial cable (approx. -27dB @ 5GHz); 1200mVP-P VIN 1600mVP-P 10Gb/s; Up to 10m 28AWG standard twin-axial cable (approx. -27dB @ 5GHz); 1200mVP-P VIN 1600mVP-P 20% to 80% From IN to OUT Time to assert Loss-of-Signal (LOS) indicator when transitioning from active data mode to line silence mode Time to de-assert Loss-of-Signal (LOS) indicator when transitioning from line silence mode to active data mode Time to transition from active data to line silence (muted output) on 10m 28AWG standard twin-axial cable at 10Gb/s Time to transition from line silence mode (muted output) to active data on 10m 28AWG standard twin-axial cable at 10Gb/s MIN 32 0.15 TYP MAX UNITS dB UI NOTES 2 1, 3, 4
SYMBOL SDC22 DJ
RJ
1.3
psRMS
1, 3, 4
tr, tf
35 500 50
ps ps s
5
6
LOS De-Assert Time
50
s
6
Data-to-Line Silence Response Time Line Silence-to-Data Response Time NOTES:
50
s
6
50
s
6
1. After channel loss, differential amplitudes at QLx111GRx input must meet the input voltage range specified in "Absolute Maximum Ratings" on page 3. 2. Temperature = +25C, VDD = 1.2V. 3. Output residual jitter is the difference between the total jitter at the lane extender output and the total jitter of the transmitted signal (as measured at the input to the channel). Total jitter (TJ) is DJpp + 14.1 x RJRMS.
4. Measured using a PRBS 27-1 pattern. Deterministic jitter at the input to the lane extender is due to frequency-dependent, media-induced loss only. 5. Rise and fall times measured using a 1GHz clock with a 20ps edge rate.
6. For active data mode, cable input amplitude is 300mVP-P (differential) or greater. For line silence mode, cable input amplitude is 20mVP-P (differential) or less.
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Typical Performance Characteristics
Performance is measured using the test setup illustrated in Figure 1. The signal from the pattern generator is launched into the twin-ax cable using an SMA adapter card. The chip evaluation board is connected to the output of the cable through another adapter card. The QLx111GRx output signal is then visualized on a scope to determine signal integrity parameters such as jitter (Note 7).
Pattern Generator
SMA Adapter Card
100O Twin-Axial Cable
SMA Adapter Card
QLx111G Eval Board
Oscilloscope
FIGURE 1. DEVICE CHARACTERIZATION SET UP
FIGURE 2. JITTER vs CABLE LENGTH AT 10Gb/s (BOOST LEVELS 0-3) NOTE:
FIGURE 3. QLx111GRx 10Gb/s OUTPUT FOR A 10M 28AWG CABLE
7. Prior to the tapeout, the data in Figures 2 and 3 represents simulations approximating the conditions of setup in Figure 1, not measured data.
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QLx111GRx
FIGURE 4. FUNCTIONAL DIAGRAM OF A SINGLE CHANNEL WITHIN THE QLx111GRx
Operation
The QLx111GRx is an advanced lane-extender for high-speed interconnects. A functional diagram of QLx111GRx is shown in Figure 4. In addition to a robust equalization filter to compensate for channel loss and restore signal fidelity, the QLx111GRx contains unique integrated features to preserve special signaling protocols typically broken by other equalizers. The signal detect function is used to mute the channel output when the equalized signal falls below the level determined by the Detection Threshold (DT) pin voltage. This function is intended to preserve periods of line silence ("quiescent state" in InfiniBand contexts). Furthermore, the output of the Signal Detect/DT comparator is used as a loss of signal (LOS) indicator to indicate the absence of a received signal. As illustrated in Figure 4, the core of the high-speed signal path in the QLx111GRx is a sophisticated equalizer followed by a limiting amplifier. The equalizer compensates for skin loss, dielectric loss, and impedance discontinuities in the transmission channel. The equalizer is followed by a limiting amplification stage that provides a clean output signal with full amplitude swing and fast rise-fall times for reliable signal decoding in a subsequent receiver.
FIGURE 5. GAIN PROFILE FOR VARIOUS BOOST SETTINGS IN QLx111GRx
Control Pin Boost Setting
The connectivity of the CP pins are used to determine the boost level of QLx111GRx. Table 1 defines the mapping from the 2-bit CP word to the 5 available boost levels.
TABLE 1. MAPPING BETWEEN BOOST LEVEL AND CPPIN CONNECTIVITY CP[A] No Connect No Connect No Connect Gnd Gnd CP[B] No Connect Gnd VDD No Connect Gnd BOOST LEVEL 0 1 2 3 4
Adjustable Equalization Boost
QLx111GRx features a settable equalizer for custom signal restoration. The flexibility of this adjustable compensation architecture enables signal fidelity to be optimized on a channel-by-channel basis, providing support for a wide variety of channel characteristics and data rates ranging from 2.5Gb/s to 11.3Gb/s. Because the boost level is externally set rather than internally adapted, the QLx111GRx provides reliable communication from the very first bit transmitted. There is no time needed for adaptation and control loop convergence. Furthermore, there are no pathological data patterns that will cause the QLx111GRx to move to an incorrect boost level.
CML Input and Output Buffers
The input and output buffers for the high-speed data channel in the QLx111GRx are implemented using CML. Equivalent input and output circuits are shown in Figures 6 and 7.
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QLx111GRx
Line Silence/Quiescent Mode
Line silence is commonly broken by the limiting amplification in other equalizers. This disruption can be detrimental in many systems that rely on line silence as part of the protocol. The QLx111GRx contains special lane management capabilities to detect and preserve periods of line silence while still providing the fidelity-enhancing benefits of limiting amplification during active data transmission. Line silence is detected by measuring the amplitude of the equalized signal and comparing that to a threshold set by the voltage at the DT pin. When the amplitude falls below the threshold, the output driver stage is muted.
LOS Indicator
Pin LOS is used to output the state of the muting circuitry to serve as a loss of signal indicator for the device. This signal is directly derived from the muting signal off the DT-threshold signal detector output. The LOS signal goes HIGH when the power signal is below the DT threshold and LOW when the power goes above the DT threshold. This feature is meant to be used in optical systems (e.g. SFP+) where there are no quiescent or electrical-idle states. In these cases, the DT threshold is used to determine the sensitivity of the LOS indicator.
FIGURE 6. CML INPUT EQUIVALENT CIRCUIT FOR THE QLx111GRx
Detection Threshold (DT) Pin Functionality
The QLx111GRx is capable of maintaining periods of line silence by monitoring each channel for loss of signal (LOS) conditions and subsequently muting the outputs of a respective channel when such a condition is detected. A reference voltage applied to the detection threshold (DT) pin is used to set the LOS threshold of the internal signal detection circuitry. Voltage control on the DT pin is done via two external resistors. Both a pull-up and pull-down resistor are tied to the DT pin, with suggested values indicated in Figure 8. Other values of the resistors may also be applicable; therefore customers are advised to verify DT settings for their specific application.
FIGURE 7. CML OUTPUT EQUIVALENT CIRCUIT FOR THE QLx111GRx
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QLx111GRx
Typical Application Reference Design
1.2V 69 50
2.5/3.3V 10k
GND
1.2V VDD
GND
LOS
DT
1.2V VDD
12
16
15
14
13
1 IN[P] IN[N] 3
OUT[P] 11
QLx111GRx Lane Extender
2
OUT[N]
10
1.2V
VDD
4 5 6 7 8 9
VDD
1.2V
GND
See Table 1 for setting for Boost Level See Table 6. CP
FIGURE 8. TYPICAL APPLICATION REFERENCE DESIGN
setting CP
FIGURE 9. TYPICAL QLx111GRx APPLICATION SCHEMATIC
8
GND
CPA
CPB
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QLx111GRx
ABOUT Q:ACTIVE(R)
Intersil has long realized that to enable the complex server clusters of next generation datacenters, it is critical to manage the signal integrity issues of electrical interconnects. To address this, Intersil has developed its groundbreaking Q:ACTIVE(R) product line. By integrating its analog ICs inside cabling interconnects, Intersil is able to achieve unsurpassed improvements in reach, power consumption, latency, and cable gauge size as well as increased airflow in tomorrow's datacenters. This new technology transforms passive cabling into intelligent "roadways" that yield lower operating expenses and capital expenditures for the expanding datacenter. Intersil Lane Extenders allow greater reach over existing cabling while reducing the need for thicker cables. This significantly reduces cable weight and clutter, increases airflow, and improves power consumption.
For additional products, see www.intersil.com/product_tree Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN6987.0 October 26, 2009
QLx111GRx
Package Outline Drawing
L16.3x3B
16 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 4/07
4X 1.5 3.00 A B 6 PIN 1 INDEX AREA 13 12X 0.50 16 6 PIN #1 INDEX AREA
12
1
3.00
1 .70
+ 0.10 - 0.15
9
4
(4X)
0.15 8 5 0.10 M C A B 4 16X 0.23 - 0.05
+ 0.07
TOP VIEW
16X 0.40 0.10
BOTTOM VIEW
SEE DETAIL "X"
0 . 90 0.1
0.10 C
C
BASE PLANE ( 2. 80 TYP ) ( 1. 70 )
SEATING PLANE 0.08 C
SIDE VIEW
( 12X 0 . 5 )
( 16X 0 . 23 )
C
0 . 2 REF
5
( 16X 0 . 60)
0 . 00 MIN. 0 . 05 MAX.
TYPICAL RECOMMENDED LAND PATTERN
DETAIL "X"
NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Reference Only. 2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994. 3. Unless otherwise specified, tolerance : Decimal 0.05 4. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 5. Tiebar shown (if present) is a non-functional feature. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature.
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